1. Field of the Invention
The present invention is generally in the field of circuit design. More specifically, the present invention is in the field of designing multi-component circuits.
2. Background Art
The demand for advanced consumer electronic devices, such as cellular phones and other wireless devices, has challenged semiconductor manufacturers to reduce the time-to-market for the integrated circuits (“IC”) these products contain. In an effort to meet that challenge, semiconductor manufacturers use automated design systems that provide the designer with sets of tools and methodologies that reduce the entire design cycle of the IC.
A typical IC design system includes a design cycle that comprises various steps. For example, the steps in an IC design cycle can include circuit design and simulation, circuit layout generation, circuit layout verification, extraction of parasitics from the circuit layout, and circuit re-simulation with the extracted parasitics. The initial circuit design and simulation is performed before the designer has knowledge of the exact layout of the entire circuit, which is generated later in the design cycle. As a result, the designer has to attempt to predict and counter the effect of various parasitics that might be introduced during layout design, which can severely degrade circuit performance.
Additionally, ICs can include multi-component circuits, such as differential pairs, differential pairs with current sources, and current mirrors that comprise two or more transistors. In addition to the parasitics generated, for example, by each transistor in a multi-component circuit, the parasitics generated by the interconnect that connects the gates, sources, and drains of each transistor in the multi-component circuit must be accurately determined to design the multi-component circuit.
Timing, voltage levels, and race conditions have to be re-verified after the designer knows of exact parasitics, such as parasitic capacitance, resistance, and inductance, extracted from circuit layout. Thus, a new circuit simulation incorporating correct values of the extracted parasitics from the circuit layout is required. Even then, the new circuit layout will often result in different values of extracted parasitics. Some parasitics may be eliminated, some new ones may be introduced, and some may increase it or decrease, as such resulting in the need to redesign and re-simulate the circuit. The above steps are repeated, where the circuit design is modified by re-extracted parasitics from the circuit layout.
Without precise knowledge of the parasitics inherent in the circuit layout, the designer has to continually attempt to predict what new parasitics might be generated from the latest circuit modifications. Thus, the circuit's design cycle continues through numerous, time consuming iterations until the circuit layout parasitics have been correctly taken into account during the circuit design and simulation cycle. This repetitious cycle can result in many days or weeks of delay in completion of the circuit design for large circuit blocks. The resulting increase in “time-to-market” causes a tremendous economic loss to semiconductor design houses and manufacturers.
FIG. 1 shows flowchart 100, which illustrates a typical sequence of steps in a circuit block's design, layout, and verification. In step 102 in FIG. 1, a circuit block is designed and a schematic for the circuit block is made. The circuit block is also simulated in step 102. The circuit block can be designed with the assistance of a commercial circuit design editor, such as Composer®, by Cadence Design Systems®, Inc. For a multi-component circuit can be input in the circuit block schematic. As a part of the circuit block design and schematic formation, parameters such as “finger width” (“WF”), “finger length” (“LF”), and “number of fingers” (“NF”) of each transistor in the multi-component circuit can be input in the circuit design editor and into the block schematic.
A simulation program can simulate the electrical behavior of a circuit block using the parameters that were input for the circuit block's components. However, the accuracy of the results obtained from the circuit simulation depend on the accuracy of all the circuit components, including a large number of parasitic components, whose values cannot generally be accurately estimated by conventional design techniques. The circuit simulation can be written and performed, for example, by using the SPECTRE® program.
In step 104, a circuit block layout is generated using a layout generator. The layout generator program can be written in SKILL®, C++, a combination of the two languages, or a combination of a number of other languages. In step 106 in FIG. 1, a design rule check (“DRC”) and a layout versus circuit schematic (“LVS”) verification is performed on the circuit block layout generated in step 104. DRC is performed to ensure that the circuit block layout conforms to all manufacturing specifications. For example, the DRC program identifies problems such as “minimum-spacing” violations and “minimum-width” violations. In LVS, the circuit block layout is checked against the circuit block schematic to ensure electrical equivalence. In other words, the circuit block layout is checked to see that it corresponds to the circuit block schematic. By way of example, the LVS checking can be implemented using the Calibre® program and a rule file written in Calibre® format.
In step 108, parasitics are extracted from the circuit block layout. For example, each transistor's “internal” parasitics and the parasitics generated by the interconnect routing between each transistor in a multi-component circuit and other circuit block components, are extracted.
It is noted that a multi-component circuit's internal parasitics have a great effect on circuit performance. The internal and interconnect routing parasitics are used by the circuit designer to modify the circuit block schematic in step 102, and the circuit design cycle comprising steps 102, 104, 106, and 108 begins anew. A modified circuit block layout is generated in step 104, and DRC and LVS are performed on the modified circuit block layout in step 106. In step 108, parasitics are extracted from the modified circuit block layout. Thus, the circuit design cycle comprising steps 102, 104, 106, and 108 as discussed above is repeated until circuit block design and simulation step 102 can be performed with a high degree of confidence in the parasitic values that correspond to the circuit block layout and, in particular, to the multi-component circuit layout. As discussed above, the repetitive circuit design cycle significantly increases the time-to-market for ICs with multi-component circuits.
Therefore, there exists a need for an integrated design system that provides a reduction in the time-to-market for integrated circuits comprising multi-component circuits. More specifically, there exists a need for an integrated design system that is able to predict the parasitics that will result from a multi-component circuit layout before the layout is generated, and thereby minimize undesirable repetition of the circuit design cycle.